Semiconductor integrated circuit

ABSTRACT

A circuit block operates while receiving a clock from an external circuit. A load balance circuit is connected to a shared power supply terminal together with the circuit block, and provides predetermined power consumption. A clock detection unit detects input of the clock from an external circuit. When the clock detection unit detects stopping of input of the clock, the load balance circuit is switched to the active state.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is the U.S. National Stage of International PatentApplication No. PCT/JP2008/001469 filed on Jun. 9, 2008 and claimspriority thereto, the disclosure of which is hereby incorporated byreference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuitconfigured to operate according to a multi-level digital signal and atest apparatus thereof, and particularly to a technique for providingstable operation of a power supply.

2. Description of the Related Art

In a case in which a semiconductor integrated circuit such as a CPU(Central Processing Unit), DSP (Digital Signal Processor), memory, etc.,which is provided using the CMOS (Complementary Metal OxideSemiconductor) technology, is tested using a semiconductor testapparatus (which will be referred to as the “test apparatus” hereafter),the test apparatus supplies a test pattern to such a semiconductorintegrated circuit, which is a device under test (which will be referredto as the “DUT” hereafter), so as to instruct the DUT to performpredetermined signal processing, and compares the data obtained as aresult of the signal processing with an expected value, therebyperforming quality judgment.

[Patent Document 1]

-   International Publication WO 06/035604 pamphlet

[Patent Document 2]

-   Japanese Patent Application Laid Open No. H11-74768

[Patent Document 3]

-   Japanese Patent Application Laid Open No. 2004-125552

[Patent Document 4]

-   Japanese Patent Application Laid Open No. 2004-125573

Upon receiving a test pattern, each flip-flop or each latch included inthe DUT performs signal processing. In this state, current consumptionoccurs. On the other hand, when the signal processing is stopped, thecircuit enters a static state, leading to reduction in the currentconsumption. Accordingly, in a case in which a test pattern isintermittently supplied to the DUT, current consumption by the DUT isalso intermittent, and current flows in a burst manner. A power supplycircuit arranged to supply power supply voltage to such a DUT isconfigured using a regulator. With an ideal power supply, such anarrangement is capable of supplying a constant power supply voltageregardless of the amount of the load current. However, in practice, sucha power supply circuit has a significant output impedance, and haslimited responsiveness to load changes. Accordingly, in a case in whichthe current consumption of the DUT changes in a burst manner, the powersupply voltage changes according to the change in the currentconsumption of the DUT.

Such change in the power supply voltage has an effect on the operationsof other circuit blocks included in the test apparatus, such as apattern generator configured to generate a pattern signal to be suppliedto the DUT, a timing generator configured to control the patterntransition timing, etc. This leads to a problem of jitter beingsuperimposed on the signal thus generated.

If there is a block that operates intermittently in the internal circuitof the test apparatus, it leads to fluctuation in the power supplyvoltage to be supplied to such a block, which is also a problem.

SUMMARY OF THE INVENTION

The present invention has been made in order to solve the aforementionedproblems. Accordingly, it is a general purpose of the present inventionto provide a semiconductor integrated circuit and a test apparatus whichare capable of suppressing fluctuation in the power supply voltageduring testing.

A semiconductor integrated circuit according to an embodiment of thepresent invention comprises: a circuit block configured to operate whilereceiving a multi-level digital signal from an external circuit; a loadbalance circuit connected to a shared power supply terminal togetherwith the circuit block, and configured to provide predetermined powerconsumption; and a detection unit configured to detect input of themulti-level digital signal from an external circuit. When the detectionunit detects stopping of input of the multi-level digital signal, theload balance circuit is switched to an active state.

When a multi-level digital signal is input to the semiconductorintegrated circuit, the semiconductor integrated circuit enters theoperation state, leading to increased current consumption. On the otherhand, its current consumption reduces when input of the multi-leveldigital signal is stopped. Thus, by detecting whether or not amulti-level digital signal is input, such an arrangement is capable ofappropriately controlling the load balance circuit. Thus, such anarrangement is capable of maintaining the current consumption of thesemiconductor integrated circuit at a constant level, therebysuppressing fluctuation in the power supply voltage.

Also, the detection unit may detect the clock signal as a multi-leveldigital signal. When a clock is input to a digital circuit, the currentconsumption of the digital circuit increases. Thus, such an arrangementis capable of appropriately controlling the load balance circuit.

Also, the detection unit may detect, as the multi-level digital signal,a binary data signal that is set to either high level or low level.Examples of such binary data signals include pseudo-random signals,address signals, and data signals.

Also, the detection unit may increase the duty ratio of each pulse ofthe multi-level digital signal to 100% or more, and may output, as asignal that indicates whether or not the multi-level signal is input, asignal including the pulses having a duty ratio thus increased.

With such an arrangement, with the pulses of the multi-level digitalsignal input in succession, the pulses having an increased duty ratioare overlapped, thereby providing a signal the level of which is fixedat high level. Thus, such an arrangement is capable of appropriatelydetecting whether or not a multi-level digital signal is input.

Also, the detection unit may comprise: multiple delay circuits; andmultiple two-input logical gates. Also, the multiple delay circuits andthe multiple two-input logical gates may be cascade-connected in analternating manner. Also, the multi-level digital signal is input to thebalance of the input terminals of the two-input logical gates.

With such an arrangement, the processing is repeatedly performed inwhich a multi-level digital signal is delayed, the resulting multi-leveldigital signal thus delayed is combined with the original multi-leveldigital signal, the multi-level digital signal thus combined is delayedagain, and the resulting multi-level digital signal thus delayed iscombined with the original multi-level digital signal. Thus, such anarrangement is capable of generating a signal having a predeterminedlevel that is fixed when the multi-level digital signal is supplied.

Also, the logical gate may generate the logical AND of two inputsignals.

Also, the semiconductor integrated circuit according to an embodimentmay further comprise: an edge detection circuit configured to detect anedge of the multi-level digital signal, and to generate a pulse sequencewhich is set to a predetermined level every time an edge is detected.Also, the pulse sequence thus generated, instead of the multi-leveldigital signal, may be input to the balance of the input terminals ofthe multiple two-input logical gates.

Such an arrangement is capable of appropriately generating a signalwhich indicates that supply of the multi-level digital signal isstopped, regardless of whether the electric potential of the multi-leveldigital signal supplied from an external circuit is fixed at low levelor high level after supply of the multi-level digital signal is stopped.

Also, the detection unit may comprise: a multi-stage delay circuitconfigured to apply multiple delay steps to the multi-level digitalsignal so as to generate multiple delayed digital signals to whichdifferent delays have been applied; and a detection processing unitconfigured to perform predetermined signal processing on the multipledelayed digital signals output from the multi-stage delay circuit so asto judge whether or not the multi-level digital signal is input.

Also, the detection processing unit may perform a logical operation onthe multiple delayed digital signals, and may output the operationresult as a detection result of whether or not input of the multi-leveldigital signal is detected.

Also, the detection processing unit may generate the logical OR of themultiple delayed digital signals.

Also, a semiconductor integrated circuit according to an embodiment mayfurther comprise an edge detection circuit configured to detect an edgeof the multi-level digital signal, and to generate a pulse sequencewhich is set to a predetermined level every time an edge is detected.Also, the multi-stage delay circuit may apply multiple delay steps tothe pulse sequence instead of to the multi-level digital signal.

Also, the detection processing unit may integrate the multiple delayeddigital signals, and may output the integration result as a detectionresult of whether or not input of the multi-level digital signal isdetected. With such an arrangement in which multiple delayed digitalsignals are integrated, the integrated value generated when themulti-level digital signal is supplied is greater than the integratedvalue generated when supply of the multi-level digital signal isstopped. Thus, such an arrangement is capable of judging, based upon theintegration result, whether or not the multi-level digital signal isinput.

Also, the load balance circuit may be configured so as to be capable ofcontrolling the power consumption thereof. Also, the semiconductorintegrated circuit may further comprise: a state detection circuitconfigured to detect the state of the semiconductor integrated circuit,and to generate a state detection signal that corresponds to the statethus detected; and a power control circuit configured to adjust thepower consumption due to the load balance circuit such that the value ofthe state detection signal when the load balance circuit is in an activestate matches the value of the state detection signal when the loadbalance circuit is in an inactive state.

By adjusting the current consumption of the load balance circuit, suchan arrangement is capable of suppressing fluctuation in the overallcurrent consumption of the semiconductor integrated circuit and the loadbalance circuit that occurs due to switching the load balance circuitbetween the active state and the inactive state.

Also, the state detection circuit may comprise: an oscillator connectedto a shared power supply terminal together with the circuit block, andconfigured to oscillate at a frequency that corresponds to the powersupply voltage at the power supply terminal; and a frequency counterconfigured to measure the frequency of the oscillator. Also, the statedetection circuit may output a state detection signal that correspondsto the frequency thus measured.

Also, the frequency counter may measure the frequency for apredetermined period after the detection unit detects stopping of inputof the multi-level digital signal so as to generate the state detectionsignal when the load balance signal is in the active state. Also, thefrequency counter may measure the frequency for a predetermined periodwhen the load balance circuit is in the inactive state so as to generatethe state detection signal when the load balance circuit is in theinactive state. Also, an arrangement may be made in which, when anexternal trigger signal is asserted, the frequency is measured for theinactive state. Also, the power control circuit may adjust the powerconsumption due to the load balance circuit such that the difference inthe frequency between the active and the inactive states of the loadbalance circuit becomes minimal.

When the state transits to the stopped state from the state in which themulti-level digital signal is supplied, the load balance circuit isturned on, and accordingly, the current consumption changes. In thisstage, in some cases, the power supply voltage fluctuates due tofluctuation in the voltage drop that occurs at the internal impedance ofthe power supply. By monitoring the state of the power supply voltageduring a fluctuation period so as to control the load balance circuit,such an arrangement is capable of appropriately suppressing fluctuationin the power supply voltage.

Another embodiment of the present invention relates to a test apparatus.The test apparatus comprises: a power supply circuit configured togenerate a power supply voltage; a multi-strobe generating unitconfigured to generate a multi-strobe signal including multiple pulseshaving edges at different timings; a circuit block configured to receivethe multi-strobe signal, and to perform predetermined signal processing;a load balance circuit configured to provided predetermined powerconsumption; and a multi-strobe detection unit configured to receive themulti-strobe signal, and to detect whether or not the multi-strobesignal is being generated by the multi-strobe generating unit. At leastthe circuit block and the load balance circuit each operate whilereceiving the shared power supply voltage. When the multi-strobedetection unit detects stopping of generation of the multi-strobesignal, the load balance circuit is set to an active state.

With such an embodiment, when the multi-strobe signal is supplied, thecurrent consumption of the circuit block increases. On the other hand,the current consumption of the circuit block reduces when supply of themulti-strobe signal is stopped. Thus, by detecting whether or not themulti-strobe signal is generated, such an arrangement is capable ofappropriately controlling the load balance circuit. Thus, such anarrangement is capable of maintaining the current consumption thatoccurs in the test apparatus, thereby suppressing fluctuation in thepower supply voltage generated by the power supply circuit. As a result,such an arrangement is capable of reducing jitter that occurs in themulti-strobe signal itself, and timing signals and pattern signalsgenerated by other circuits.

Also, the multi-strobe detection unit may output, as a detection result,the logical OR of the multiple pulses included in the multi-strobesignal.

Also, the multi-strobe detection unit may integrate the multiple pulsesincluded in the multi-strobe signal, and may output the integrationresult as a detection result.

Also, the load balance circuit may be configured so as to be capable ofcontrolling the power consumption thereof. Also, the test apparatus mayfurther comprise: a state detection unit configured to detect the stateof the semiconductor integrated circuit, and to generate a statedetection signal that corresponds to the state thus detected; and apower control circuit configured to adjust power consumption due to theload balance circuit such that the value of the state detection signalwhen the load balance circuit is in the active state matches the valueof the state detection signal when the load balance circuit is in theinactive state.

Also, the state detection circuit may comprise: an oscillator configuredto operate while receiving the power supply voltage; and a frequencycounter configured to measure the frequency of the oscillator. Also, thestate detection circuit may output the state detection signal thatcorresponds to the frequency thus measured.

Also, the frequency counter may measure the frequency for apredetermined period after the multi-strobe detection unit detectsstopping of generation of the multi-strobe signal, so as to generate thestate detection signal when the load balance circuit is in the activestate. Also, the frequency counter may measure the frequency for apredetermined period when the load balance circuit is in the inactivestate, so as to generate the state detection signal when the loadbalance circuit is in the inactive state. Also, an arrangement may bemade in which, when an external trigger signal is asserted, thefrequency is measured for the inactive state. Also, the power controlcircuit may adjust the power consumption due to the load balance circuitsuch that the difference in the frequency between the active and theinactive state of the load balance circuit becomes minimal.

Also, the circuit block may latch the input data with each edge of themulti-strobe signal. Also, the circuit block may perform processing oneach data thus latched.

It is to be noted that any arbitrary combination or rearrangement of theabove-described structural components and so forth is effective as andencompassed by the present embodiments.

Moreover, this summary of the invention does not necessarily describeall necessary features so that the invention may also be asub-combination of these described features.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will now be described, by way of example only, withreference to the accompanying drawings which are meant to be exemplary,not limiting, and wherein like elements are numbered alike in severalFigures, in which:

FIG. 1 is a circuit diagram which shows a configuration of asemiconductor integrated circuit according to a first embodiment;

FIG. 2 is a circuit diagram which shows an example configuration of aclock detection unit and a load balance circuit;

FIG. 3 is a time chart which shows the operation of the clock detectionunit shown in FIG. 2;

FIG. 4 is a circuit diagram which shows a configuration of a clockdetection unit according to a modification;

FIG. 5 is a time chart which shows a load regulation operation of thesemiconductor integrated circuit shown in FIG. 1; and

FIG. 6 is a block diagram which shows a configuration of a semiconductortest apparatus according to a second embodiment.

DETAILED DESCRIPTION OF THE INVENTION

Description will be made below regarding preferred embodiments accordingto the present invention with reference to the drawings. The same orsimilar components, members, and processes are denoted by the samereference numerals, and redundant description thereof will be omitted asappropriate. The embodiments have been described for exemplary purposesonly, and are by no means intended to restrict the present invention.Also, it is not necessarily essential for the present invention that allthe features or a combination thereof be provided as described in theembodiments.

In the present specification, a state represented by the phrase “themember A is connected to the member B” includes a state in which themember A is indirectly connected to the member B via another member thatdoes not affect the electric connection therebetween, in addition to astate in which the member A is physically and directly connected to themember B.

Description will be made in a first embodiment regarding a semiconductorintegrated circuit having a mechanism for suppressing fluctuation in thevoltage of a power supply provided as a built-in component of a testapparatus during testing. Next, description will be made regarding atest apparatus having a mechanism for suppressing fluctuation in thepower supply voltage due to current consumption that occurs in theinternal circuit of the test apparatus.

First Embodiment

FIG. 1 is a circuit diagram which shows a configuration of asemiconductor integrated circuit 100 according to the first embodiment.FIG. 1 also shows a test apparatus 200 configured to test thesemiconductor integrated circuit 100, in addition to the semiconductorintegrated circuit 100.

The semiconductor integrated circuit 100 includes a power supplyterminal 102 configured to receive a power supply voltage Vdd, a clockterminal 104 configured to receive a clock CLK, a data input terminal106 configured to receive data S1 from an external circuit, and a dataoutput terminal 108 configured to output data S2 to an external circuit.The semiconductor integrated circuit 100 is configured as a function IC(Integrated Circuit) integrated on a single semiconductor substrate.

The semiconductor integrated circuit 100 includes a circuit block 10, aclock detection unit 20, a load balance circuit 40, a state detectioncircuit 44, and a power control circuit 46.

The circuit block 10 is a circuit configured to itself execute theoperation of the semiconductor integrated circuit, and performspredetermined signal processing using a received power supply voltageVdd and a clock CLK. The configuration and the operation of the circuitblock 10 are not restricted in particular. That is to say, thesemiconductor integrated circuit 100 may be configured as any of a CPU,DSP, or memory, or as another kind of digital circuit or digital/analoghybrid circuit.

The load balance circuit 40 is connected to the shared power supplyterminal 102 together with the circuit block 10, and providespredetermined power (current) consumption. The load balance circuit 40is arranged as a dummy load (current source) provided in order tomaintain at a constant level the current supplied from an externalcircuit via the power supply terminal 102. The load balance circuit 40has a configuration which allows the state to be switched between an ONstate (active state) and an OFF state (inactive state) according to anenable signal EN supplied from an external circuit.

The clock detection unit 20 detects input of the clock CLK supplied froman external circuit. The clock detection unit 20 generates the enablesignal EN which is set to a predetermined level (high level) when itdetects the clock CLK.

That is to say, when the clock detection unit 20 detects input of theclock CLK, the load balance circuit 40 enters the active state. In theactive state, the load balance circuit 40 provides current consumption(which will be referred to as “balance current Ibal” hereafter).

In many cases, the clock detection unit 20, the load balance circuit 40,the state detection circuit 44, and the power control circuit 46 areeach a circuit that is used during testing. Also, these components maybe used in a state in which the semiconductor integrated circuit 100 canbe mounted on an end product.

The above is the basic configuration of the semiconductor integratedcircuit 100. Description will be made regarding the operation of thesemiconductor integrated circuit 100 during testing. During testing, thesemiconductor integrated circuit 100 is mounted on a socket board(performance board) of the test apparatus 200. The test apparatus 200includes a power supply circuit 202 configured to generate the powersupply voltage Vdd to be supplied to the semiconductor integratedcircuit 100 which is a DUT, a test signal generating unit 204 configuredto supply a test signal S1 to the DUT, and a judgment unit 206configured to perform quality judgment. The semiconductor integratedcircuit 100 receives the test signal S1 supplied from the test signalgenerating unit 204, and performs predetermined signal processing. Thetest apparatus 200 reads out data S2 obtained as a result of the signalprocessing. The judgment unit 206 makes a comparison between an expectedvalue that corresponds to the test signal S1 and the signal S2 thusgenerated by the semiconductor integrated circuit 100, thereby judgingthe quality of the semiconductor integrated circuit 100.

When the semiconductor integrated circuit 100 is tested, a clock CLK,which is used to operate the semiconductor integrated circuit 100, isoutput together with, or independent of, the test data S1.

When the semiconductor integrated circuit 100 performs signal processingusing the input clock CLK, an amount of current Idd is consumed in thecircuit block 10. When the operation of the semiconductor integratedcircuit 100 is stopped, it reduces consumption of the current Idd thatoccurs in the circuit block 10. In this stage, if the load balancecircuit 40 is not operated, the load as seen from the power supplycircuit 202 side becomes light, leading to fluctuation in the powersupply voltage Vdd. Such fluctuation in the power supply voltage Vddleads to jitter being superimposed on various kinds of signals generatedby the test signal generating unit 204.

The clock detection unit 20 of the semiconductor integrated circuit 100judges whether or not the clock CLK is input. The clock detection unit20 instructs the load balance circuit 40 to enter the active stateduring a period in which input of the clock CLK is stopped, i.e., duringa period in which the operation of the circuit block 10 is stopped. As aresult, the reduction in the current Idd due to the stopping of theoperation of the circuit block 10 is canceled out by the balance currentIbal that flows through the load balance circuit 40. This maintains theload as seen from the power supply circuit 202 at a constant level. As aresult, such an arrangement is capable of suppressing fluctuation in thepower supply voltage Vdd, thereby providing stable operation of the testsignal generating unit 204.

FIG. 2 is a circuit diagram which shows example configurations of theclock detection unit 20 and the load balance circuit 40. The clockdetection unit 20 includes an input buffer 22, an output buffer 24,multiple NAND gates NAND1 through NAND8, multiple OR gates OR1 throughOR8, and multiple delay circuits DLY1 through DLY7 (a part of thesecomponents is not shown).

The input buffer 22 and the multiple NAND gates (NAND1 through NAND8)are arranged to distribute the clock CLK, and to independently switch onand off the clocks thus distributed. With the circuit shown in FIG. 2,the clock CLK is divided into a maximum of eight distributed clocks. Thenumber of distributed clocks matches the number of OR gates arranged asdownstream components.

The clock CLK is distributed to the multiple NAND gates via the inputbuffer 22. A control signal XCNT is input to the other input terminal ofeach of the gates NAND1 through NAND8. The control signal XCNT is storedin the register 26, and its level can be set via an external circuit.With attention to the i-th NAND gate NANDi, when the control signalXCNT[i−1] is low level, the path of the i-th NAND gate NANDi isdisabled, thereby preventing the clock CLK from being distributed to thedownstream components.

The multiple OR gates and the multiple delay circuits DLY1 through DLY7are cascade-connected in an alternating manner. That is to say, the i-thdelay circuit DLYi receives, as an input signal, the output signal CLKiof the i-th OR gate ORi. The output signal (which will also be referredto as the “delayed clock”) CLKdi of the i-th delay circuit DLYi is inputto one input terminal of the (i+1)-th OR gate.

The OR gates OR1 through OR8 receive, as input signals and via the otherterminals thereof, the respective clocks distributed by the gates NAND1through NAND8. The output signal of the final-stage OR gate OR8 isoutput as an enable signal EN via the output buffer 24.

FIG. 3 is a time chart which shows the operation of the clock detectionunit 20 shown in FIG. 2. The output signal CLKi of the i-th OR gate isdelayed by a predetermined period of time τ by means of the i-th delaycircuit DLYi. The next-stage OR gate OR(i+1) calculates the logical ORof the delayed clock CLKid and the original clock CLK. By sequentiallyperforming this processing in increments of i, the original clock CLK issubjected to smoothing processing, thereby generating the enable signalEN.

That is to say, the clock detection unit 20 repeatedly performs theprocessing in which the delayed clock CLK is combined with the originalclock CLK, the clock thus combined is delayed again, and the combinedclock thus delayed is combined with the original clock. Thus, the clockdetection unit 20 is capable of generating a signal which is set to apredetermined level while the clock is supplied.

Also, by inverting the signals, an arrangement may be made employingother kinds of two-input logical gates instead of the OR gates, therebyproviding the same functions.

Referring to the time chart shown in FIG. 3, the clock detection unit 20shown in FIG. 2 can be understood to be a circuit configured to generatepulses obtained by delaying the clock CLK, and to integrate theresulting pulses.

Seen from a different point of view, the following comprehensive conceptcan be understood of the clock detection operation of the clockdetection unit 20. That is, the clock detection unit 20 stretches theduty ratio of each pulse of the clock CLK to 100% or more. With such anarrangement, the clock detection unit 20 outputs a signal including thepulses with an increased width as a signal (EN) that indicates whetheror not input of the clock CLK is detected.

Returning to FIG. 2, the enable signal EN is supplied to the loadbalance circuit 40 arranged as a downstream circuit. The load balancecircuit 40 includes multiple (for example, ten) load circuits HT each ofwhich is capable of independently switching on and off, and AND gatesAND1 through AND10 provided in increments of load circuits HT. The loadbalance circuit 40 is configured so as to have controllable powerconsumption. Each load circuit HT generates heat using electric power.Accordingly, the load circuit HT will be referred to as a “heater”. Whenthe output of the AND gate is high level, the corresponding heater HT isturned on, and when the output of the AND gate is low level, thecorresponding heater HT is turned off.

The enable signal EN is input to one input terminal of each of themultiple AND gates AND1 through AND10. The multiple AND gates AND1through AND10 receive, via their other input terminals, respectivecontrol signals HT[0] through HT[9]. The control signal HT[9:0] isstored in a register 42, and its level can be set via an externalcircuit. With attention to the i-th heater HTi, when the control signalHT[i−1] is low level, the i-th heater HTi is turned off regardless ofthe enable signal EN. When the control signal HT[i−1] is high level, theON/OFF operation of the i-th heater HTi is controlled according to thelevel of the enable signal EN.

For example, with the unit of current consumption as 1, the currentconsumption provided by the multiple load circuits HT can be set to 1,2, 4, . . . , 256, and 512. With such an arrangement, the overallcurrent consumption provided by the load balance circuit 40 can becontrolled to 1024 levels according to the 10-bit control signalHT[9:0]. Furthermore, the multiple heaters HT each receive, as an inputsignal, a power down control signal PC. Upon receiving the power downcontrol signal PC, the load balance circuit 40 is turned off regardlessof the register settings HT[9:0] and the enable signal EN. After thesemiconductor integrated circuit 100 is mounted on an end product, byfixing the power down control signal PC at low level, such anarrangement is capable of forcibly stopping the operation of the loadbalance circuit 40.

The clock detection unit 20 shown in FIG. 2 normally operates in acondition in which the clock CLK is fixed at low level when it is in thestopped state. If the clock CLK is fixed at high level in the stoppedstate, the enable signal EN, which is to be fixed at low level in thisstate, is set to high level. This leads to a malfunction of the loadbalance circuit 40. In order to solve such a problem, an edge detectioncircuit 28 is provided, which enables the load balance circuit 40 tonormally operate regardless of whether the clock CLK is fixed at highlevel or low level.

The edge detection circuit 28 detects an edge of the clock CLK, andgenerates a pulse sequence PS which is set to a predetermined level(high level) every time an edge is detected. A selector 29 selectseither the clock CLK or the pulse sequence PS supplied from the edgedetection circuit 28, and outputs the signal thus selected to the clockdetection unit 20.

The pulse sequence PS, instead of the clock CLK, is input to theabove-mentioned other input terminals of the multiple two-input logicalgates (OR gates) via the input buffer 22 and the NAND gates. Byselecting the pulse sequence PS by means of the selector 29, such anarrangement is capable of setting the enable signal EN to low level evenif the clock CLK supplied from an external circuit is fixed at highlevel in the stopped state.

It should be noted that, in a case in which the clock CLK is fixed atlow level in the state in which supply of the clock CLK is stopped, anarrangement may be made which does not include the edge detectioncircuit 28 and the selector 29. Conversely, in a case in which the clockCLK is fixed at high level in the state in which supply of the clock CLKis stopped, an arrangement may be made including only the edge detectioncircuit 28. It is needless to say that, with an arrangement includingthe edge detection circuit 28 and the selector 29 as shown in FIG. 2,such an arrangement is capable of appropriately detecting whether or notthe clock is input regardless of whether the logical value of the clockCLK is high level or low level in the stopped state of the clock CLK.

The same operation as that of the clock detection unit 20 shown in FIG.2 can also be realized by means of a clock detection unit 20 a shown inFIG. 4. FIG. 4 is a circuit diagram which shows a configuration of theclock detection unit 20 a according to a modification.

The clock detection unit 20 a includes a multi-stage delay circuit 30and a detection processing unit 32.

The multi-stage delay circuit 30 applies multiple delay steps to theclock CLK, thereby generating multiple delayed clocks CLKd0 throughCLKdn to which different respective delays have been applied. Thedetection processing unit 32 performs predetermined signal processing onthe multiple delayed clocks CLKd so as to judge whether the clock CLK isinput. In a most simple configuration, the detection processing unit 32can be configured as an OR gate. However, an arrangement may be madeusing other circuits.

Also, with the clock detection unit 20 a shown in FIG. 4, whether or notthe clock CLK is input can be appropriately judged in the same way aswith the clock detection unit 20 shown in FIG. 2. The circuit shown inFIG. 2 repeatedly performs the delay processing and the predeterminedsignal processing (OR operation) in an alternating manner. In contrast,the circuit shown in FIG. 4 generates the delayed clocks CLKd at thesame time, and the operation is performed once on the delayed clocksCLKd thus generated. That is to say, the difference in the operationbetween the clock detection unit 20 a and the clock detection unit 20 isonly in the order of the signal processing. The operations of the clockdetection unit 20 a and the clock detection unit 20 are substantiallythe same.

With a modification shown in FIG. 4, the edge detection circuit 28 shownin FIG. 2 may be arranged as an upstream component of the multi-stagedelay circuit 30.

With attention to the operations of the circuits shown in FIG. 4 andFIG. 2, such a circuit repeatedly performs the processing in which aclock to which delay has been applied is combined with the originalclock. That is to say, the operation of the clock detection unit 20 canbe understood as processing for integrating the clocks. Seen from thispoint of view, the operation of the detection processing unit 32 shownin FIG. 4 can also be understood as an operation in which the multipledelayed clocks CLKd0 through CLKdn are integrated, and the resultingsignal thus integrated is output as a detection result.

Next, returning to FIG. 1, description will be made regarding atechnique for appropriately controlling the power consumption of theload balance circuit 40 in a case in which it is controllable.

The state detection circuit 44 detects the state of the semiconductorintegrated circuit 100, and generates a state detection signal S3 thatcorresponds to the state thus detected.

The power control circuit 46 adjusts the power consumption provided bythe load balance circuit 40 such that the value of the state detectionsignal S3 when the load balance circuit 40 is in the active statematches the value of the state detection signal S3 when the load balancecircuit 40 is in the inactive state. The adjustment of the powerconsumption is performed by writing data to the register 42 shown inFIG. 2.

By controlling the current consumption amount of the load balancecircuit 40 in addition to switching on and off the load balance circuit40, such an arrangement is capable of suppressing fluctuation of theoverall current consumption of the semiconductor integrated circuit andthe load balance circuit that occurs due to switching the load balancecircuit between the active state and the inactive state.

As the state detection circuit 44, a ring oscillator can be suitablyemployed, the oscillation frequency of which changes according to thepower supply voltage Vdd and the temperature of the semiconductorintegrated circuit 100. With such an arrangement, the state detectioncircuit 44 may be connected to the shared power supply terminal 102together with the circuit block 10. Also, the state detection circuit 44may include a frequency counter (not shown) configured to measure thefrequency of the ring oscillator. The value of the frequency measured bythe frequency counter is output to the power control circuit 46 as thestate detection signal S3.

FIG. 5 is a time chart which shows load regulation provided by thesemiconductor integrated circuit 100 shown in FIG. 1. During a period inwhich the clock CLK is input, consumption of the current Idd occurs inthe circuit block 10. The current Idd has ripples that are synchronouswith the clock CLK. When the clock CLK is stopped, the load balancecircuit 40 enters the active state, thereby maintaining consumption ofthe current Idd at a constant level. At the timing at which the loadbalance circuit 40 switches from off to on, an overshoot of the powersupply voltage Vdd occurs. Such an overshoot occurs on the time order of100 μs to several ms.

Also, an arrangement may be made in which, during a predetermined periodT2 after the clock detection unit 20 detects stopping of input of theclock CLK, the frequency counter measures the frequency so as togenerate the state detection signal S3 when the load balance circuit 40is in the active state. Furthermore, the frequency counter measures thefrequency during a predetermined period T1 in which the clock CLK isinput, and generates the state detection signal S3 when the load balanceis in the inactive state. The power control circuit 46 controls theamount of current generated by the balance circuit 40 such that thestate detection signals S3 thus acquired in these two periods T1 and T2match each other.

When the state is switched from the state in which the clock CLK isstopped to the state in which the clock CLK is supplied, the currentconsumption fluctuates, leading to large fluctuation in the power supplyvoltage. By monitoring the state of the power supply voltage Vdd duringa period in which it fluctuates, such an arrangement is capable ofsuitably suppressing fluctuation in the power supply voltage Vdd.

Description has been made in the first embodiment regarding anarrangement in which, with the semiconductor integrated circuit 100according to the first embodiment, upon detecting stopping of input ofthe clock CLK, the load balance circuit 40 is switched to the activestate. However, the present invention is not restricted to such anarrangement.

For example, an arrangement may be made in which input of a data signalsuch as a pseudo-random signal is detected instead of the clock CLK. Thesame detection method as that for detecting the clock CLK may beemployed in such an arrangement. For example, where a pseudo randomsignal is input to the circuit, the density of the data transitionpoints (edges) changes in a random manner, leading to fluctuation in thecurrent consumption of the circuit. In order to solve such a problem, bydetecting such a pseudo random signal so as to control the load balancecircuit 40 instead of the clock, such an arrangement is capable ofcanceling out the fluctuation in the current consumption that occurs dueto irregularities in the density of the data signal. Thus, such anarrangement is capable of suppressing fluctuation in the power supplyvoltage supplied to the semiconductor integrated circuit 100.

Also, with a circuit employing the CDR (Clock Data Recovery) method, theclock is reproduced based upon edges embedded in the data signal. Withsuch an arrangement, detection of input of the data signal is equivalentto detection of the clock. Thus, such an arrangement is capable ofmaintaining current consumption at a constant level, thereby suppressingfluctuation in the power supply voltage.

Second Embodiment

FIG. 6 is a block diagram which shows a configuration of a semiconductortest apparatus 200 according to a second embodiment. The test apparatus200 includes a power supply circuit 50, a multi-strobe generating unit52, a circuit block 54, a load balance circuit 56, and a multi-strobedetection unit 58.

The power supply circuit 50 is configured as a regulator or the like,and generates a power supply voltage Vdd. The multi-strobe generatingunit 52 generates a multi-strobe signal MSTRB. The multi-strobe signalMSTRB includes multiple pulses having edges at different timings. Themulti-strobe signal is generated by applying multiple delay steps to asingle input strobe signal by means of the multi-stage delay circuit 30as shown in FIG. 4.

The circuit block 54 receives the multi-strobe signal MSTRB, andperforms predetermined signal processing. The content of the signalprocessing is not restricted in particular. Examples of such signalprocessing include an arrangement disclosed in Japanese PatentApplication Laid Open No. 2004-125552 and an arrangement disclosed inJapanese Patent Application Laid Open No. 2004-125573.

The circuit block 54 includes a comparator 60, a latch circuit 62, and atransition point detection unit 64. The comparator 60 receives, as aninput signal, a data signal DQ output from an unshown DUT. Thecomparator 60 compares the data signal DQ with a predetermined thresholdvoltage, thereby performing level judgment. The latch circuit 62 latchesthe signal S4, which represents the judgment result, at a timing of eachpulse edge included in the multi-strobe signal MSTRB. As a result, thevalue of the data S5 thus latched changes with the level transitionpoint of the data signal DQ as a boundary. The transition pointdetection unit detects the timing of the transition point of the datasignal DQ based upon the data S5 thus latched. For example, by measuringthe transition point for a certain number of data signals DQ, such anarrangement is capable of measuring jitter. By repeatedly performingsuch a test, such an arrangement is capable of performing eye marginmeasurement.

The load balance circuit 56 receives the shared power supply voltage Vddin the same way as the circuit block 54, and consumes a predeterminedamount of electric power. The function and the purpose of the loadbalance circuit 56 are the same as those of the load balance circuit 40described in the first embodiment with reference to FIG. 1.

The multi-strobe signal MSTRB is also supplied to the multi-strobedetection unit 58. The multi-strobe detection unit 58 detects whether ornot the multi-strobe signal MSTRB is being generated by the multi-strobegenerating unit 52. When the multi-strobe detection unit 58 detectsstopping of generation of the multi-strobe signal MSTRB, themulti-strobe detection unit 58 sets the enable signal EN to apredetermined level (high level), which switches the load balancecircuit 56 to the active state (on).

When the multi-strobe signal MSTRB is supplied, the current consumptionof the circuit block 54 increases, and its current consumption reduceswhen supply of the multi-strobe signal MSTRB is stopped. Thus, bydetecting whether or not the multi-strobe signal MSTRB is generated,such an arrangement is capable of appropriately controlling the loadbalance circuit 40. Thus, such an arrangement is capable of maintainingthe current consumption that occurs in the test apparatus 200, therebysuppressing fluctuation in the power supply voltage Vdd generated by thepower supply circuit 50. As a result, such an arrangement is capable ofreducing jitter that occurs in the multi-strobe signal itself, andtiming signals and pattern signals generated by other circuits.

As described above, the multi-strobe signal MSTRB is a signal which isequivalent to the multiple delayed clock CLKd generated by themulti-stage delay circuit 30 shown in FIG. 4. Thus, by calculating thelogical OR of the pulses included in the multi-strobe signal MSTRB inthe same way as the detection processing unit 32 shown in FIG. 4, themulti-strobe detection unit 58 is capable of generating the enablesignal EN.

Alternatively, the multi-strobe detection unit 58 may integrate thepulses included in the multi-strobe signal MSTRB, and may output theintegration result as the enable signal EN.

Also, the edge detection circuit 28 as described in the first embodimentmay be applied to the second embodiment. Also, by packaging the statedetection circuit 44 and the power control circuit 46 in the testapparatus 200, such an arrangement provides further stabilization of thepower supply.

Description has been made regarding the present invention with referenceto the embodiment. The above-described embodiment has been described forexemplary purposes only, and is by no means intended to be interpretedrestrictively. Rather, it can be readily conceived by those skilled inthis art that various modifications may be made by making variouscombinations of the aforementioned components or processes, which arealso encompassed in the technical scope of the present invention.Description will be made below regarding such modifications.

Description has been made in the first embodiment regarding anarrangement in which the semiconductor integrated circuit 100 is to betested by the test apparatus 200. Also, the semiconductor integratedcircuit 100 itself may be configured as a function IC as a built-incomponent packaged in the test apparatus 200. In a case in which thetest apparatus 200 includes an internal circuit block configured tooperate while receiving a clock, by employing the semiconductorintegrated circuit 100 shown in FIG. 1, such an arrangement is capableof maintaining a load on the power supply circuit 202 even if the clockis stopped.

Description has been made regarding the present invention with referenceto the embodiments. However, the above-described embodiments show onlythe mechanisms and applications of the present invention for exemplarypurposes only, and are by no means intended to be interpretedrestrictively. Rather, various modifications and various changes in thelayout can be made without departing from the spirit and scope of thepresent invention defined in appended claims.

1. A semiconductor integrated circuit comprising: a circuit blockconfigured to operate while receiving a multi-level digital signal froman external circuit; a load balance circuit connected to a shared powersupply terminal together with the circuit block, and configured toprovide predetermined power consumption; and a detection unit configuredto detect input of the multi-level digital signal from an externalcircuit, wherein, when the detection unit detects stopping of input ofthe multi-level digital signal, the load balance circuit is switched toan active state.
 2. A semiconductor integrated circuit according toclaim 1, wherein the multi-level digital signal is configured as a clocksignal.
 3. A semiconductor integrated circuit according to claim 1,wherein the multi-level digital signal is configured as a binary datasignal that is set to either high level or low level.
 4. A semiconductorintegrated circuit according to claim 1, wherein the detection unitincreases the duty ratio of each pulse of the multi-level digital signalto 100% or more, and outputs, as a signal that indicates whether or notthe multi-level signal is input, a signal including the pulses having aduty ratio thus increased.
 5. A semiconductor integrated circuitaccording to claim 1, wherein the detection unit comprises: a pluralityof delay circuits; and a plurality of two-input logical gates, whereinthe plurality of delay circuits and the plurality of two-input logicalgates are cascade-connected in an alternating manner, and wherein themulti-level digital signal is input to the balance of the inputterminals of the two-input logical gates.
 6. A semiconductor integratedcircuit according to claim 5, wherein the logical gate generates thelogical AND of two input signals.
 7. A semiconductor integrated circuitaccording to claim 4, further comprising: an edge detection circuitconfigured to detect an edge of the multi-level digital signal, and togenerate a pulse sequence which is set to a predetermined level everytime an edge is detected, and wherein the pulse sequence thus generated,instead of the multi-level digital signal, is input to the balance ofthe input terminals of the plurality of two-input logical gates.
 8. Asemiconductor integrated circuit according to claim 1, wherein thedetection unit comprises: a multi-stage delay circuit configured toapply a plurality of delay steps to the multi-level digital signal so asto generate a plurality of delayed digital signals to which differentdelays have been applied; and a detection processing unit configured toperform predetermined signal processing on the plurality of delayeddigital signals output from the multi-stage delay circuit so as to judgewhether or not the multi-level digital signal is input.
 9. Asemiconductor integrated circuit according to claim 8, wherein thedetection processing unit generates the logical OR of the plurality ofdelayed digital signals, and outputs the calculation result as adetection result of whether or not input of the multi-level digitalsignal is detected.
 10. A semiconductor integrated circuit according toclaim 8, further comprising: an edge detection circuit configured todetect an edge of the multi-level digital signal, and to generate apulse sequence which is set to a predetermined level every time an edgeis detected, wherein the multi-stage delay circuit applies multipledelay steps to the pulse sequence instead of to the multi-level digitalsignal.
 11. A semiconductor integrated circuit according to claim 8,wherein the detection processing unit integrates the plurality ofdelayed digital signals, and outputs the integration result as adetection result of whether or not input of the multi-level digitalsignal is detected.
 12. A semiconductor integrated circuit according toclaim 1, wherein the load balance circuit is configured so as to becapable of controlling the power consumption thereof, and wherein thesemiconductor integrated circuit further comprises: a state detectioncircuit configured to detect the state of the semiconductor integratedcircuit, and to generate a state detection signal that corresponds tothe state thus detected; and a power control circuit configured toadjust the power consumption due to the load balance circuit such thatthe value of the state detection signal when the load balance circuit isin an active state matches the value of the state detection signal whenthe load balance circuit is in an inactive state.
 13. A semiconductorintegrated circuit according to claim 12, wherein the state detectioncircuit comprises: an oscillator connected to a shared power supplyterminal together with the circuit block, and configured to oscillate ata frequency that corresponds to the power supply voltage at the powersupply terminal; and a frequency counter configured to measure thefrequency of the oscillator, wherein the state detection circuit outputsa state detection signal that corresponds to the frequency thusmeasured.
 14. A semiconductor integrated circuit according to claim 13,wherein the frequency counter measures the frequency for a predeterminedperiod after the detection unit detects stopping of input of themulti-level digital signal so as to generate the state detection signalwhen the load balance signal is in the active state, and wherein thefrequency counter measures the frequency for a predetermined period whenthe load balance circuit is in the inactive state so as to generate thestate detection signal when the load balance circuit is in the inactivestate, and wherein the power control circuit adjusts the powerconsumption due to the load balance circuit such that the difference inthe frequency between the active and the inactive states of the loadbalance circuit becomes minimal.
 15. A test apparatus comprising: apower supply circuit configured to generate a power supply voltage; amulti-strobe generating unit configured to generate a multi-strobesignal including a plurality of pulses having edges at differenttimings; a circuit block configured to receive the multi-strobe signal,and to perform predetermined signal processing; a load balance circuitconfigured to provided predetermined power consumption; and amulti-strobe detection unit configured to receive the multi-strobesignal, and to detect whether or not the multi-strobe signal is beinggenerated by the multi-strobe generating unit, wherein at least thecircuit block and the load balance circuit each operate while receivingthe shared power supply voltage, and wherein, when the multi-strobedetection unit detects stopping of generation of the multi-strobesignal, the load balance circuit is set to an active state.
 16. A testapparatus according to claim 15, wherein the multi-strobe detection unitoutputs, as a detection result, the logical OR of the plurality ofpulses included in the multi-strobe signal.
 17. A test apparatusaccording to claim 15, wherein the multi-strobe detection unitintegrates the plurality of pulses included in the multi-strobe signal,and outputs the integration result as a detection result.
 18. A testapparatus according to claim 15, wherein the load balance circuit isconfigured so as to be capable of controlling the power consumptionthereof, and wherein the test apparatus further comprises: a statemeasurement unit configured to detect the state of the semiconductorintegrated circuit, and to generate a state detection signal thatcorresponds to the state thus detected; and a power control circuitconfigured to adjust power consumption due to the load balance circuitsuch that the value of the state detection signal when the load balancecircuit is in the active state matches the value of the state detectionsignal when the load balance circuit is in the inactive state.
 19. Atest apparatus according to claim 18, wherein the state detectioncircuit comprises: an oscillator configured to operate while receivingthe power supply voltage; and a frequency counter configured to measurethe frequency of the oscillator, wherein the state detection circuitoutputs the state detection signal that corresponds to the frequencythus measured.
 20. A test apparatus according to claim 19, wherein thefrequency counter measures the frequency for a predetermined periodafter the multi-strobe detection unit detects stopping of generation ofthe multi-strobe signal, so as to generate the state detection signalwhen the load balance circuit is in the active state, and wherein thefrequency counter measures the frequency for a predetermined period whenthe load balance circuit is in the inactive state, so as to generate thestate detection signal when the load balance circuit is in the inactivestate, and wherein the power control circuit adjusts the powerconsumption due to the load balance circuit such that the difference inthe frequency between the active and the inactive state of the loadbalance circuit becomes minimal.
 21. A test apparatus according to claim15, wherein the circuit block latches the input data with each edge ofthe multi-strobe signal, and wherein the circuit block performsprocessing on each data thus latched.